COM-HPC: Reaching a Higher (Performance) Standard

What you’ll learn

  • What’s new with NXP’s S32K3 series.
  • How lockstep makes a difference with the S32K3.

NXP Semiconductors has used the Cortex-M7 core for a range of automotive microcontroller units (MCUs) starting with the S32K1 series. The new S32K3 series raises all the bars with more memory and performance as well as including features like lockstep mode (Fig. 1). Asymmetric Cortex systems-on-chip (SoCs) are common, but they’re typically a Cortex-M0+ and a higher-end Cortex-M or combined with a Cortex-A application processor. There are single-core S32K3s, but dual- and triple-core versions exist as well, running up to 240 MHz.

1. The S32K3 family scales from a single-core Cortex-M7 through a triple- or dual-core lockstep system.

The S32K family targets automotive applications. They have up to 8 MB of flash and up to 256 kB SRAM memory with ECC support. The flash is setup as two blocks that allow an A/B firmware swap with automatic address translation. Firmware-over-the-air (FOTA) updates load into one block while the system runs from the other block. The switch occurs on reset with the ability to fallback to the original block if there are problems.

The chips are designed for safety-critical applications that meet ISO 26262 ASIL B/D requirements. The family has a fault collection and control unit with an HSE-B security engine that supports AES-128/192/256, RSA, and ECC. This also provides secure boot with key storage and side-channel attack protection. It’s intended to support ISO 21434 automotive security.

The systems have QSPI and serial ports as well as I3C, I2C, and up to eight CAN FD ports. The 10/100-Mb/s Ethernet supports time sensitive networking (TSN) and audio video bridging (AVB). Up to three 24-channel, 12-bit ADCs are available. The 16-bit eMIOS (enhanced modular input/output system) timer with logic control unit can handle motor-control chores.

The S32K3 family comes in BGA and MaxQFP packages (Fig. 2). The MaxQFP is 55% smaller than a conventional QFP while retaining the same number of pins. The architecture uses conventional QFP pins on the outside and a wraparound pin on the edge of the chip. The latter’s solder pad is partially under the chip. There are 10- × 10-mm, 100-pin chips as well as 16- × 16-mm, 172-pin versions of MaxQFP, allowing for pin-compatible replacements using most of the available S32K3 devices. High-pin-count devices are also available in MAPBGA-289 packages.

2. The MaxQFP package (left) reduces the chip footprint by more than 50% (top right). Half of the pins have a conventional QFP layout, while the other half curve under the chip (bottom right).2. The MaxQFP package (left) reduces the chip footprint by more than 50% (top right). Half of the pins have a conventional QFP layout, while the other half curve under the chip (bottom right).

The hardware is impressive, but software costs often dominate many automotive designs. To this end, NXP provides free ISO 26262-compliant real-time software drivers for AUTOSAR and non-AUTOSAR. They used to provide the latter. Given that most of these chips will need to meet ASIL A/B requirements, the free AUTOSAR drivers can save a significant chunk of change.

The drivers are all part of NXP’s software package that also includes the Safety Framework Software and Core Self-Test library. The framework integrates over half a dozen modules supporting everything from lockstep operation to security, obviously taking advantage of the underlying hardware.

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