It’s a new weekend, and I’m back to my obsession with stepper motors. If you haven’t read part one of this series yet, go back and read it here. That’s not an order; more of a plea.
In any case, I’ve nearly completed the schematic now. It’s got four sheets. One for the FPGA, one for the stepper driver, one for the power supply, and one for switches and indicators. I haven’t yet put the switches in the schematic, because my choice of switch – both the type and number – will be determined by the amount of available PCB space. At 42 mm square, with four mounting holes and three integrated circuits, it might be a tight squeeze.
Here, we have the PC board and all of the components, except switches, ready to be placed.
It should all fit, but it won’t be the easiest route I’ve ever done.
Step one is usually placing the connectors, but first, I wanted to check out the footprints on the QFNs. That is, after all, what got me started on this. The QFN footprint is different from most in that it needs special care regarding the solder paste layer (sometimes called stencil layer). If the entire thermal pad area is full of paste, the QFN will most likely float up too high to connect with all of the paste blobs on the connections running around the outside of the package.
I checked the footprints for the QFNs here. All three of them have thermal vias in the center pad – open thermal vias. Open vias in a pad are not good. It’s quite likely that some of the solderpaste will wick down into the via, ending up on the bottom side of the PCB. Ironically, that might mitigate the float problem, but it may cause other problems, like shorts, or even insufficient solder under your QFNs.
These vias need to be filled or capped. The solder paste stencil needs to be segmented to give between 50% and 75% paste coverage, (and to keep paste off of the vias if the vias are capped with solder mask). Read more about the QFN stencil layer here and here. I’m really not sure why, a decade since becoming popular, QFN footprints so rarely get the stencil layer right. I’ll have to fix those.
Maybe in traditional manufacturing, that’s all settle out in the NPI (new product introduction) process. But, so much of today’s electronics no longer get built that way. We’re often asked to build 100 boards in a week, or a half dozen overnight. With that kind of timescale, this type of issue needs to be found and fixed in minutes or hours rather than days or weeks (or better yet, in the design, before being sent to manufacturing).
Even the component manufacturers often ignore the paste layer. A few will specify such details as capped or uncapped vias and the need for segmented stencil, but many others don’t even mention the stencil, despite it being one of the most important factors in manufacturability.
Stay tuned for my next entry in the saga of the sad solder stencil.
I bet Starman capped his vias